This patent claims the benefit of U.S. Ser. No. 61/823,312 filed May 14, 2013, the entire disclosure of which is hereby incorporated by reference.
The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
ICs are commonly formed by a sequence of material layers, some of which are patterned by a photolithography process. It is important that the patterned layers properly align or overlay with adjacent layers. Proper alignment and overlay becomes more difficult in light of the decreasing geometry sizes of modern ICs. In addition, the surface topography of an underlying substrate, such as a semiconductor wafer, impacts the lithography imaging quality and further degrades the overlay tolerance between adjacent material layers. Furthermore, lithography processes are a significant contributor to the overall cost of manufacturing, including processing time and the cost of masks (also referred to as photomasks) used in the process. Therefore, what is needed is a lithography method to address the above issues.